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| data sheet 1997, 2000 mos integrated circuit m pd784224, 784225, 784224y, 784225y 16/8-bit single-chip microcontrollers the m pd784224 and 784225 are products of the m pd784225 subseries in the 78k/iv series. besides a high- speed and high performance cpu, these controllers have rom, ram, i/o ports, 8-bit resolution a/d and d/a converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral hardware. the m pd784224y and 784225y are based on the m pd784225 subseries with the addition of a multimaster- supporting i 2 c bus interface. flash memory versions, the m pd78f4225 and 78f4225y, which replace the internal rom of the mask rom version with flash memory, and various development tools are also available. the functions are explained in detail in the following users manuals. be sure to read this manual when designing your system. m pd784225, 784225y subseries users manual - hardware : u12697e 78k/iv series users manual - instruction : u10905e features ?i 2 c bus ? rom correction ? inherits peripheral functions of m pd780058y subseries ? minimum instruction execution time 160 ns (main system clock f xx = 12.5 mhz) 61 m s (subsystem clock f xt = 32.768 khz) ? i/o port: 67 pins ? timer/counter: 16-bit timer/counter 1 unit 8-bit timer/counter 4 units ? serial interface: 3 channels uart/ioe (3-wire serial i/o): 2 channels csi (3-wire serial i/o, multi-master supporting i 2 c bus note ): 1 channel note m pd784225y subseries only ? standby function halt/stop/idle mode in power-saving mode: halt/idle mode (with subsystem clock) ? clock division function ? watch timer: 1 channel ? watchdog timer: 1 channel ? clock output function f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt selectable ? buzzer output function f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 selectable ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? supply voltage: v dd = 1.8 to 5.5 v document no. u12376ej1v0ds00 (1st edition) date published may 2000 j cp(k) printed in japan application field car audio, portable audio, telephones, etc. unless contextually excluded, references in this document to m pd784225 mean m pd784224, 784225, 784224y, and 784225y. the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version.
2 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 ordering information part number package internal rom (bytes) internal ram (bytes) m pd784224gc- -8bt 80-pin plastic qfp (14 14 mm) 96 k 3,584 m pd784224gk- -9eu note 80-pin plastic tqfp (fine pitch) (14 20 mm) 96 k 3,584 m pD784225GC- -8bt 80-pin plastic qfp (14 14 mm) 128 k 4,352 m pd784225gk- -9eu 80-pin plastic tqfp (fine pitch) (14 20 mm) 128 k 4,352 m pd784224ygc- -8bt 80-pin plastic qfp (14 14 mm) 96 k 3,584 m pd784224ygk- -9eu 80-pin plastic tqfp (fine pitch) (14 20 mm) 96 k 3,584 m pd784225ygc- -8bt note 80-pin plastic qfp (14 14 mm) 128 k 4,352 m pd784225ygk- -9eu note 80-pin plastic tqfp (fine pitch) (14 20 mm) 128 k 4,352 note under development remark indicates a rom code suffix. 3 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 78k/iv series lineup pd784026 pd784956a pd784908 pd784915 pd784928 pd784928y pd784046 pd784054 pd784216a pd784216ay pd784038 pd784038y pd784225y pd784225 pd784218ay pd784218a enhanced a/d converter, 16-bit timer, and power management enhanced internal memory capacity pin-compatible with the pd784026 supports i 2 c bus supports multi-master i 2 c bus 80-pin, rom correction added supports multi-master i 2 c bus enhanced internal memory capacity, rom correction added 100-pin, enhanced i/o and internal memory capacity on-chip 10-bit a/d converter for dc inverter control on-chip iebus tm controller software servo control on-chip analog circuit for vcrs enhanced timer supports multi-master i 2 c bus enhanced functions of the pd784915 standard models assp models supports multi-master i 2 c bus : in mass production : under development m m pd784967 on-chip fip controller/driver m m m m m m m m m m m m m m m m m pd784938a enhanced functions of the pd784908, enhanced internal memory capacity, rom correction added. m m 4 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 functions part number m pd784224, m pd784225, item m pd784224y m pd784225y number of basic instructions 113 (mnemonics) general-purpose register 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution ? 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: f xx = 12.5 mhz) time ? 61 m s (subsystem clock: f xt = 32.768 khz) internal rom 96 kbytes 128 kbytes memory ram 3,584 bytes 4,352 bytes memory space 1 mb with program and data spaces combined i/o port total 67 cmos input 8 cmos i/o 59 pins with pull-up 57 resistor leds direct 16 drive output real-time output port 4 bits 2, or 8 bits 1 timer timer/event counter : timer counter 1 pulse output (16-bit) capture/compare register 2 ? pwm/ppg output ? square wave output ? one-shot pulse output timer/event counter 1 : timer counter 1 pulse output (8-bit) compare register 1 ? pwm output ? square wave output timer/event counter 2 : timer counter 1 pulse output (8-bit) compare register 1 ? pwm output ? square wave output timer 5 : timer counter 1 (8-bit) compare register 1 timer 6 : timer counter 1 (8-bit) compare register 1 serial interface ? uart/ioe (3-wire serial i/o): 2 channels ( on-chip baud rate generator ) ? csi (3-wire serial i/o, i 2 c bus note 2 supporting multi master): 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels clock output selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt buzzer output selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 watch timer 1 channel watchdog timer 1 channel standby ? halt/stop/idle mode ? in power-saving mode (with subsystem clock): halt/idle mode interrupt hardware 25 (internal: 18, external: 7) software brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 17, external: 6 ? 4 programmable priority levels ? 3 service modes: vectored interrupt/macro service/context switching supply voltage v dd = 1.8 to 5.5 v package ? 80-pin plastic qfp(14 14 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm) notes 1. the pins with ancillary functions are included in the i/o pins. 2. m pd784225y subseries only pins with ancillary functions note 1 5 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 contents 1. differences among models in m pd784225, 784225y subseries .............................. 7 2. major differences between m pd784216y subseries and m pd780058y subseries ............................................................................................................. 8 3. pin configuration (top view) ............................................................................................... 9 4. block diagram ........................................................................................................................ 11 5. pin function ............................................................................................................................... 12 5.1 port pins ............................................................................................................................... ................. 12 5.2 pins other than port pins .................................................................................................................. 14 5.3 i/o circuit type of respective pins and recommended connections of unused pins ........... 16 6. cpu architecture ................................................................................................................... 20 6.1 memory space ............................................................................................................................... ....... 20 6.2 cpu registers ............................................................................................................................... ....... 23 6.2.1 general-purpose registers ................................................................................................. ......... 23 6.2.2 control registers ......................................................................................................... ................. 24 6.2.3 special function registers (sfrs) ......................................................................................... ...... 25 7. peripheral hardware functions .................................................................................... 30 7.1 ports ............................................................................................................................... ........................ 30 7.2 clock generator ............................................................................................................................... .... 31 7.3 real-time output port ......................................................................................................................... 33 7.4 timer ............................................................................................................................... ....................... 34 7.5 a/d converter ............................................................................................................................... ........ 37 7.6 d/a converter ............................................................................................................................... ........ 38 7.7 serial interface ............................................................................................................................... ...... 39 7.7.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) ...................................................... 40 7.7.2 clocked serial interface (csi) ............................................................................................ ......... 42 7.8 clock output function ........................................................................................................................ 43 7.9 buzzer output function ...................................................................................................................... 44 7.10 edge detection function .................................................................................................................... 44 7.11 watch timer ............................................................................................................................... ........... 44 7.12 watchdog timer ............................................................................................................................... .... 45 8. interrupt function ................................................................................................................ 46 8.1 interrupt sources ............................................................................................................................... .. 46 8.2 vectored interrupt ............................................................................................................................... .48 8.3 context switching ............................................................................................................................... .49 8.4 macro service ............................................................................................................................... ........ 49 8.5 application example of macro service ............................................................................................. 50 6 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 9. local bus interface ............................................................................................................. 51 9.1 memory expansion .............................................................................................................................. 5 1 9.2 programmable wait ............................................................................................................................. 51 9.3 external access status function ...................................................................................................... 51 10. standby function ................................................................................................................... 52 11. reset function ......................................................................................................................... 54 12. rom correction ...................................................................................................................... 55 13. instruction set ........................................................................................................................ 56 14. electrical specifications ................................................................................................. 61 15. package drawings ................................................................................................................. 82 16. recommended soldering conditions ............................................................................ 84 appendix a. development tools ............................................................................................ 85 appendix b. related documents ............................................................................................ 88 7 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 1. differences among models in m pd784225, 784225y subseries the only difference among the m pd784224 and 784225 lies in the internal memory capacity. the m pd784224y and 784225y are based on the m pd784224 and 784225 respectively, with the addition of an i 2 c bus control function. the m pd78f4225 and 78f4225y are provided with a 128-kbyte flash memory instead of the mask rom of the above models. these differences are summarized in table 1-1. table 1-1. differences among models in m pd784225, 784225y subseries part number m pd784224, m pd784225, m pd78f4225, item m pd784224y m pd784225y m pd78f4225y internal rom 96 kbytes 128 kbytes 128 kbytes (mask rom) (mask rom) (flash memory) internal ram 3,584 bytes 4,352 bytes internal memory none provided size switching register (ims) note supply voltage v dd = 1.8 to 5.5 v v dd = 1.9 to 5.5 v electrical refer to the data sheet for each device. specifications recommended soldering conditions test pin provided none v pp pin none provided note the internal flash memory capacity and internal ram capacity can be changed using the internal memory size switching register (ims). caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask rom version. 8 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 2. major differences between m pd784216y subseries and m pd780058y subseries series name m pd784225, 784225y m pd784216y subseries m pd780058y subseries item subseries cpu 16-bit cpu 8-bit cpu minimum with main system 160 ns (at 12.5 mhz) 400 ns (at 5.0 mhz) instruction clock selected execution time with subsystem 61 m s (at 32.768 khz) 122 m s (at 32.768 khz) clock memory space 1 mbytes 64 kbytes i/o port total 67 pins 86 pins 68 pins cmos input 8 pins 8 pins 2 pins cmos i/o 59 pins 72 pins 62 pins n-ch open-drain i/o - 6 pins 4 pins pins with pins with pull-up 57 pins 70 pins 66 pins (flash memory ancillary resistor model: 62 pins) function note 1 led direct drive 16 pins 22 pins 12 pins output medium-voltage pin - 6 pins 4 pins timer/counter ? 16-bit timer/event counter ? 16-bit timer/event counter ? 16-bit timer/event counter 1 unit 1 unit 1 unit ? 8-bit timer/event counter ? 8-bit timer/event counter ? 8-bit timer/event counter 4 units 6 units 2 units serial interface ? uart/ioe (3-wire serial i/o) 2 channels ? uart (time-division transfer ? csi (3-wire serial i/o, multi-master supporting i 2 c function)/ioe (3-wire bus note 2 ) 1 channel serial i/o) 2 channels ? csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus) 1 channel ? csi (3-wire serial i/o with automatic transmission/reception function) 1 channel interrupt nmi pin provided none macro service provided none context switching provided none programmable priority 4 levels 2 levels standby function ? halt/stop/idle mode halt/stop mode ? power-saving mode: halt/idle mode rom correction provided none provided package ? 80-pin plastic qfp ? 100-pin plastic qfp ? 80-pin plastic qfp (14 14 mm) (fine pitch) (14 14 mm) (14 14 mm) ? 80-pin plastic tqfp ? 100-pin plastic qfp ? 80-pin plastic tqfp (fine pitch) (12 12 mm) (14 20 mm) (fine pitch) (12 12 mm) notes 1. pins with ancillary function are included in the i/o pins. 2. m pd784225y and 784216y subseries only 9 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 3. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) m pd784224gc- -8bt, m pd784224ygc- -8bt, m pD784225GC- -8bt, m pd784225ygc- -8bt 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd784224gk- -be9, m pd784224ygk- -be9, m pd784225gk- -be9, m pd784225ygk- -be9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd2 p71/so2/txd2 p72/sck2/asck2 p20/si1/rxd1 p21/so1/txd1 p22/sck1/asck1 p23/pcl p24/buz p25/si0/sda0 note 1 p26/so0 p27/sck0/scl0 note 1 p40/ad0 p41/ad1 reset p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rpt2 p121/rtp1 p120/rtp0 p37/exa p36/ti01 p35/ti00 p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss1 p56/a14 p57/a15 p60/a16 p61/a17 p62/a18 p63/a19 p64/rd 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 21 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 a14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av dd v dd0 xt1 xt2 test note 2 x1 x2 v dd1 v ss0 p05/intp5 p04/intp4 p03/intp3 p02/intp2/nmi p01/intp1 p00/intp0 notes 1. the scl0 and sda0 pins are available in m pd784225y subseries only. 2. connect the test pin to v ss0 directly or via a pull-down resistor. for the pull-down connection, use of a resistor with a resistance ranging from 470 w to 10 k w is recommended. caution connect the av ss pin to v ss0 . remark when using in applications where noise from inside the microcomputer has to be reduced, it is recommended to take countermeasures against noise such as supplying power to v dd0 and v dd1 independently, and connecting v ss0 and v ss1 to different ground lines. 10 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 a8 to a19 : address bus ad0 to ad7 : address/data bus ani0 to ani7 : analog input ano0, ano1 : analog output asck1, asck2 : asynchronous serial clock astb : address strobe av dd : analog power supply av ref1 : analog reference voltage av ss : analog ground buz : buzzer clock exa : external access status output intp0 to intp5 : interrupt from peripherals nmi : non-maskable interrupt p00 to p05 : port0 p10 to p17 : port1 p20 to p27 : port2 p30 to p37 : port3 p40 to p47 : port4 p50 to p57 : port5 p60 to p67 : port6 p70 to p72 : port7 p120 to p127 : port12 p130, p131 : port13 pcl : programmable clock rd : read strobe reset : reset rtp0 to rtp7 : real-time output port rxd1, rxd2 : receive data sck0 to sck2 : serial clock scl0 note : serial clock sda0 note : serial data si0 to si2 : serial input so0 to so2 : serial output test : test ti00, ti01, ti1, ti2 : timer input to0 to to2 : timer output txd1, txd2 : transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait : wait wr : write strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) note the scl0 and sda0 pins are available in m pd784225y subseries only. 11 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 4. block diagram intp2/nmi intp0, intp1, intp3 to intp5 programmable interrupt controller real-time output port timer/counter6 (8 bits) timer/counter5 (8 bits) timer/event counter2 (8 bits) timer/event counter1 (8 bits) timer/event counter (16 bits) watch timer watchdog timer ti00 ti01 to0 ti1 to1 ti2 to2 rtp0 to rtp7 clock output control a/d converter av dd av ss pcl buz ani0 to ani7 d/a converter ano0 av ss av ref1 ano1 78k/iv cpu core rom ram baud-rate generator rxd1/si1 txd1/so1 asck1/sck1 rxd2/si2 txd2/so2 asck2/sck2 si0/sda0 note so0 sck0/scl0 note bus i/f uart/ioe1 rd astb wr wait ad0 to ad7 a8 to a15 a16 to a19 port1 p10 to p17 port0 port2 p20 to p27 port3 p30 to p37 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port7 p70 to p72 port12 p120 to p127 port13 p130, p131 buzzer output system control reset xt2 x1 xt1 x2 v ss0 , v ss1 v dd0 , v dd1 test clocked serial interface baud-rate generator uart/ioe2 exa p00 to p05 nmi/intp2 p03/intp3 note this function supports the i 2 c bus interface and is available in m pd784225y subseries only. remark the internal rom and ram capacities differ depending on the model. 12 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 5. pin function 5.1 port pins (1/2) pin name i/o alternate function function p00 i/o intp0 p01 intp1 p02 intp2/nm1 p03 intp3 p04 intp4 p05 intp5 p10 to p17 input ani0 to ani7 p20 i/o rxd1/si1 p21 txd1/so1 p22 asck1/sck1 p23 pcl p24 buz p25 si0/sda0 note p26 so0 p27 sck0/scl0 note p30 i/o to0 p31 to1 p32 to2 p33 ti1 p34 ti2 p35 ti00 p36 ti01 p37 exa p40 to p47 i/o ad0 to ad7 port 4 (p4): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? all pins set in input mode can be connected to internal pull-up resistors by software. ? can drive leds. p50 to p57 i/o a8 to a15 port 5 (p5): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? all pins set in input mode can be connected to internal pull-up resistors by software. ? can drive leds. note this function is available in m pd784255y subseries only. port 1 (p1): ? 8-bit input port port 0 (p0): ? 6-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistors by software bit-wise. port 2 (p2): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistors by software bit-wise. port 3 (p3): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistors by software bit-wise. 13 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 5.1 port pins (2/2) pin name i/o alternate function function p60 i/o a16 p61 a17 p62 a18 p63 a19 p64 rd p65 wr p66 wait p67 astb p70 i/o rxd2/si2 p71 txd2/so2 p72 asck2/sck2 p120 to p127 i/o rtp0 to rtp7 port 12 (p12): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistor by software bit-wise. p130, p131 i/o ano0, ano1 port 13 (p13): ? 2-bit i/o port ? can be set in input or output mode bit-wise. port 6 (p6): ? 8-bit i/o port ? can be set in input or output mode bit-wise. ? all pins set in input mode can be connected to internal pull-up resistors by software. port 7 (p7): ? 3-bit i/o port ? can be set in input or output mode bit-wise. ? pins set in input mode can be connected to internal pull-up resistor by software bit-wise. 14 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 5.2 pins other than port pins (1/2) pin name i/o alternate function function ti00 input p35 external count clock input to 16-bit timer register ti01 p36 capture trigger signal input to capture/compare register 00 ti1 p33 external count clock input to 8-bit timer register 1 ti2 p34 external count clock input to 8-bit timer register 2 to0 output p30 16-bit timer output (shared by 14-bit pwm output) to1 p31 8-bit timer output (shared by 8-bit pwm output) to2 p32 rxd1 input p20/si1 serial data input (uart1) rxd2 p70/si2 serial data input (uart2) txd1 output p21/so1 serial data output (uart1) txd2 p71/so2 serial data output (uart2) asck1 intput p22/sck1 baud rate clock input (uart1) asck2 p72/sck2 baud rate clock input (uart2) si0 input p25/sda0 note serial data input (3-wire serial clock i/o0) si1 p20/rxd1 serial data input (3-wire serial clock i/o1) si2 p70/rxd2 serial data input (3-wire serial clock i/o2) so0 output p26 serial data output (3-wire serial i/o0) so1 p21/txd1 serial data output (3-wire serial i/o1) so2 p71/txd2 serial data output (3-wire serial i/o2) sda0 note i/o p25/si0 serial data input/output (i 2 c bus) sck0 i/o p27/scl0 note serial clock input/output (3-wire serial i/o0) sck1 p22/asck1 serial clock input/output (3-wire serial i/o1) sck2 p72/asck2 serial clock input/output (3-wire serial i/o2) scl0 note p27/sck0 serial clock input/output (i 2 c bus) nmi input p02/intp2 non-maskable interrupt request input intp0 p00 external interrupt request input intp1 p01 intp2 p02/nmi intp3 p03 intp4 p04 intp5 p05 pcl output p23 clock output (for trimming main system clock and subsystem clock) buz output p24 buzzer output rtp0 to rtp7 output p120 to p127 real-time output port that outputs data in synchronization with trigger ad0 to ad7 i/o p40 to p47 low-order address/data bus when external memory is connected a8 to a15 output p50 to p57 middle-order address bus when external memory is connected a16 to a19 p60 to p63 high-order address bus when external memory is connected note this function is available in m pd784255y subseries only. 15 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 5.2 pins other than port pins (2/2) pin name i/o alternate function function rd output p64 strobe signal output for read operation of external memory wr p65 strobe signal output for write operation of external memory wait input p66 to insert wait state(s) when external memory is accessed astb output p67 strobe output to externally latch address information output to ports 4 to 6 to access external memory exa output p37 external access status output reset input - system reset input x1 input - to connect main system clock oscillation crystal x2 - xt1 input - to connect subsystem clock oscillation crystal xt2 - ani0 to ani7 input p10 to p17 analog voltage input for a/d converter ano0, ano1 output p130, p131 analog voltage output for d/a converter av ref1 -- to apply reference voltage for d/a converter av dd positive power supply for a/d converter. connected to v dd0 . av ss gnd for a/d converter and d/a converter. connected to v ss0 . v dd0 positive power supply for port block v ss0 gnd potential for port block v dd1 positive power supply (except port block) v ss1 gnd potential (except port block) test connect this pin to v ss0 directly or via pull-down resistor. for the pull-down connection, use of a resistor with a resistance ranging from 470 w to 10 k w is recommended. 16 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 5.3 i/o circuit type of respective pins and recommended connections of unused pins table 5-1 shows symbols indicating the i/o circuit types of the respective pins and the recommended connection of unused pins. for the circuit diagram of each type of i/o circuit, refer to figure 5-1 . table 5-1. i/o circuit type of respective pins and recommended connections of unused pins (1/2) pin name i/o circuit type i/o recommended connections of unused pins p00/intp0 8-k i/o input : individually connected to v ss0 via resistor p01/intp1 output: open p02/intp2/nmi p03/intp3 to p05/intp5 p10/ani0 to p17/ani7 9 input connected to v ss0 or v dd0 p20/rxd1/si1 10-i i/o input : individually connected to v ss0 via resistor p21/txd1/so1 10-j output: open p22/asck1/sck1 10-i p23/pcl 10-j p24/buz p25/sda0 note /si0 10-i p26/so0 10-j p27/scl0 note /sck0 10-i p30/to0 to p32/to2 8-m p33/ti1, p34/ti2 8-k p35/ti00, p36/ti01 8-l p37/exa 8-m p40/ad0 to p47/ad7 5-h p50/a8 to p57/a15 p60/a16 to p63/a19 p64/rd p65/wr p66/wait p67/astb p70/rxd2/si2 8-k p71/txd2/so2 8-l p72/asck2/sck2 8-k note this function is available in m pd784255y subseries only. remark because the circuit type numbers are standardized among the 78k series products, they are not sequential in some models (i.e., some circuits are not provided). 17 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 table 5-1. i/o circuit type of respective pins and recommended connections of unused pins (2/2) pin name i/o circuit type i/o recommended connections of unused pins p120/rtp0 to p127/rtp7 8-k i/o input : individually connected to v ss0 via resistor p130/ano0, p131/ano1 12-d output: open reset 2-g input - xt1 16 connected to v ss0 xt2 - open av ref1 - connected to v dd0 av dd av ss connected to v ss0 test/v pp note directly connected to v ss0 note v pp pin is available in m pd78f4225, 78f4255y only. remark because the circuit type numbers are standardized among the 78k series products, they are not sequential in some models (i.e., some circuits are not provided). 18 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 5-1. types of pin i/o circuits (1/2) type 2-g type 5-h type 8-k type 8-m type 10-i type 9 type 10-j type 8-l in schmitt trigger input with hysteresis characteristics pullup enable data output disable input enable v dd0 p-ch v dd0 v ss0 v ss0 p-ch in/out n-ch pullup enable data output disable v dd0 p-ch v dd0 p-ch in/out n-ch in comparator + - v ref (threshold voltage) p-ch n-ch input enable v ss0 pullup enable data open drain output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 pullup enable data open drain output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 pullup enable data open drain output disable v dd0 p-ch v dd0 p-ch in/out n-ch pullup enable data output disable input enable v dd0 p-ch v dd0 v ss0 p-ch in/out n-ch 19 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 5-1. types of pin i/o circuits (2/2) v ss0 v ss0 type 12-d data output disable input enable analog output voltage v dd0 p-ch in/out n-ch p-ch n-ch type 16 feedback cut-off p-ch xt1 xt2 20 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 6. cpu architecture 6.1 memory space a memory space of 1 mbyte can be accessed. mapping of the internal data area (special function registers and internal ram) can be specified the location instruction. the location instruction must be always executed after reset cancellation, and must not be used more than once. (1) when location 0h instruction is executed ? internal memory the internal data area and internal rom area are mapped as follows: part number internal data area internal rom area m pd784224, 0f100h to 0ffffh 00000h to 0f0ffh m pd784224y 10000h to 17fffh m pd784225, 0ee00h to 0ffffh 00000h to 0edffh m pd784225y 10000h to 1ffffh caution the following areas that overlap the internal data area of the internal rom cannot be used when the location 0h instruction is executed. part number unusable area m pd784224, 0f100h to 0ffffh (3,840 bytes) m pd784224y m pd784225, 0ee00h to 0ffffh (4,608 bytes) m pd784225y ? external memory the external memory is accessed in external memory expansion mode. (2) when location 0fh instruction is executed ? internal memory the internal data area and internal rom area are mapped as follows: part number internal data area internal rom area m pd784224, ff100h to fffffh 00000h to 17fffh m pd784224y m pd784225, fee00h to fffffh 00000h to 1ffffh m pd784225y ? external memory the external memory is accessed in external memory expansion mode. 21 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 6-1. memory map of m pd784224, 784224y notes 1. accessed in external memory expansion mode. 2. this 3,840-byte area can be used as an internal rom only when the location 0fh instruction is executed. 3. on execution of location 0h instruction: 94,464 bytes, on execution of location 0fh instruction: 98,304 bytes 4. base area and entry area for reset or interrupt. however, the internal ram area is not used as a reset entry area. internal rom (61,696 bytes) (256 bytes) special function registers (sfr) internal ram (3,584 bytes) external memory note 1 (928 kbytes) note 1 general-purpose registers (128 bytes) macro service control word area (52 bytes) data area (512 bytes) program/data area (3,072 bytes) callf entry area (2 kbytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (3,584 bytes) external memory note 1 (980,736 bytes) (256 bytes) internal rom (96 kbytes) on execution of location 0h instruction special function registers (sfr) note 1 on execution of location 0fh instruction h f f f f f h 0 0 0 0 1 h f f f f 0 h f d f f 0 h 0 d f f 0 h 0 0 f f 0 h f f e f 0 h 0 0 1 f 0 h f f 0 f 0 h 0 0 0 0 0 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h 9 3 e f 0 h 0 0 d f 0 h f f c f 0 h 6 0 e f 0 h 0 0 1 f 0 h f f f 7 1 h 0 0 0 1 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h 0 4 0 0 0 h f 3 0 0 0 h 0 0 0 0 0 h f f e f f h 0 8 e f f h f 7 e f f h 9 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 7 f f h 0 0 0 0 0 h f f f 7 1 h 0 0 0 8 1 h f f 0 f f h 0 0 1 f f h f f f f f h f d f f f h 0 d f f f h 0 0 f f f h f f e f f note 4 note 4 note 2 h f f f 7 1 h 0 0 0 8 1 h f f f 7 1 internal rom (32,768 bytes) h f f 0 f 0 h 0 0 0 0 1 22 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 6-2. memory map of m pd784225, 784225y notes 1. accessed in external memory expansion mode. 2. this 4,608-byte area can be used as an internal rom only when the location 0fh instruction is executed. 3. on execution of location 0h instruction: 126,464 bytes, on execution of location 0fh instruction: 131,072 bytes 4. base area and entry area for reset or interrupt. however, the internal ram area is not used as a reset entry area. internal rom (60,928 bytes) (256 bytes) special function registers (sfr) internal ram (4,352 bytes) external memory note 1 (896 kbytes) note 1 general-purpose registers (128 bytes) macro service control word area (52 bytes) data area (512 bytes) program/data area (3,840 bytes) callf entry area (2 kbytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (4,352 bytes) external memory note 1 (912,896 bytes) (256 bytes) internal rom (128 kbytes) on execution of location 0h instruction special function registers (sfr) note 1 on execution of location 0fh instruction h f f f f f h 0 0 0 0 1 h f f f f 0 h f d f f 0 h 0 d f f 0 h 0 0 f f 0 h f f e f 0 h 0 0 e e 0 h f f d e 0 h 0 0 0 0 0 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h 9 3 e f 0 h 0 0 d f 0 h f f c f 0 h 6 0 e f 0 h 0 0 e e 0 h 0 0 0 1 0 h f f f 0 0 h 0 0 8 0 0 h f f 7 0 0 h 0 8 0 0 0 h f 7 0 0 0 h 0 4 0 0 0 h f 3 0 0 0 h 0 0 0 0 0 h f f e f f h 0 8 e f f h f 7 e f f h 9 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 e e f h 0 0 0 0 0 h f f f f 1 h 0 0 0 0 2 h f f d e f h 0 0 e e f h f f f f f h f d f f f h 0 d f f f h 0 0 f f f h f f e f f note 4 note 4 h f f f f 1 internal rom (65,536 bytes) h 0 0 0 0 2 h f f f f 1 h f f f f 1 note 2 h f f d e 0 h 0 0 0 0 1 23 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 6.2 cpu registers 6.2.1 general-purpose registers sixteen 8-bit general-purpose registers are available. two 8-bit registers can be also used in pairs as a 16-bit register. of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers. eight banks of these registers are available which can be selected by using software or the context switching function. the general-purpose registers except v, u, t, and w registers for address expansion are mapped to the internal ram. figure 6-3. general-purpose register format a (r1) b (r3) r5 r7 r9 r11 d (r13) h (r15) v u t w vvp (rg4) uup (rg5) tde (rg6) whl (rg7) x (r0) c (r2) r4 r6 r8 r10 e (r12) l (r14) ax (rp0) bc (rp1) rp2 rp3 vp (rp4) up (rp5) de (rp6) hl (rp7) parentheses ( ) indicate an absolute name. 8 banks caution registers r4, r5, r6, r7, rp2, and rp3 can be used as x, a, c, b, ax, and bc registers, respectively, by setting the rss bit of the psw to 1. however, use this function only for recycling the program of the 78k/iii series. 24 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 6.2.2 control registers (1) program counter (pc) the program counter is a 20-bit register whose contents are automatically updated when the program is executed. figure 6-4. program counter (pc) format 19 0 pc (2) program status word (psw) this register holds the statuses of the cpu. its contents are automatically updated when the program is executed. figure 6-5. program status word (psw) format 15 14 13 12 11 10 9 8 uf rbs2 rbs1 rbs0 C C C C pswh 76 54 3210 s z rss note ac ie p/v 0 cy pswl psw note this flag is provided to maintain compatibility with the 78k/iii series. be sure to clear this flag to 0, except when the software for the 78k/iii series is used. (3) stack pointer (sp) this is a 24-bit pointer that holds the first address of the stack. be sure to write 0 to the higher 4 bits of this pointer. figure 6-6. stack pointer (sp) format 23 0 pc 20 0 0 0 0 25 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 6.2.3 special function registers (sfrs) the special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. these registers are mapped to a 256-byte space of addresses 0ff00h to 0ffffh note . note on execution of the location 0h instruction. fff00h to fffffh on execution of the location 0fh instruction. caution do not access an address in this area to which no sfr is allocated. if such an address is accessed by mistake, the m pd784225 may be in the deadlock status. this deadlock status can be cleared only by inputting the reset signal. table 6-1 lists the special function registers (sfrs). the meanings of the symbols in this table are as follows: ? symbol ............................... symbol indicating an sfr. this symbol is reserved for necs assembler (ra78k4). it can be used an sfr variable by the #pragma sfr directive with the c compiler (cc78k4). ? r/w .................................... indicates whether the sfr is read-only, write-only, or read/write. r/w : read/write r : read-only w : write-only ? bit units for manipulation .. bit units in which the value of the sfr can be manipulated. sfrs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. to specify the address of this sfr, describe an even address. sfrs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. ? at reset .............................. indicates the status of the register when the reset signal has been input. 26 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 table 6-1. special function register (sfr) list (1/4) address note 1 special function register (sfr) name symbol r/w bit units for manipulation at reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w 00h note 2 0ff01h port 1 p1 r 0ff02h port 2 p2 r/w 0ff03h port 3 p3 0ff04h port 4 p4 0ff05h port 5 p5 0ff06h port 6 p6 0ff07h port 7 p7 0ff0ch port 12 p12 0ff0dh port 13 p13 0ff10h 16-bit timer counter tm0 r 0000h 0ff11h 0ff12h capture/compare register 00 cr00 r/w 0ff13h (16-bit timer/counter) 0ff14h capture/compare register 01 cr01 0ff15h (16-bit timer/counter) 0ff16h capture/compare control register 0 crc0 00h 0ff18h 16-bit timer mode control register tmc0 0ff1ah 16-bit timer output control register toc0 0ff1ch prescaler mode register 0 prm0 0ff20h port 0 mode register pm0 ffh 0ff22h port 2 mode register pm2 0ff23h port 3 mode register pm3 0ff24h port 4 mode register pm4 0ff25h port 5 mode register pm5 0ff26h port 6 mode register pm6 0ff27h port 7 mode register pm7 0ff2ch port 12 mode register pm12 0ff2dh port 13 mode register pm13 0ff30h pull-up resistor option register 0 pu0 00h 0ff32h pull-up resistor option register 2 pu2 0ff33h pull-up resistor option register 3 pu3 0ff37h pull-up resistor option register 7 pu7 0ff3ch pull-up resistor option register 12 pu12 0ff40h clock output control register cks notes 1. when the location 0h instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. because each port is initialized to input mode at reset, 00h is not actually read. the output latch is initialized to 0. 27 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 table 6-1. special function register (sfr) list (2/4) address note special function register (sfr) name symbol r/w bit units for manipulation at reset 1 bit 8 bits 16 bits 0ff42h port function control register pf2 r/w 00h 0ff4eh pull-up resistor option register puo 0ff50h 8-bit timer counter 1 tm1 tm1w r 0000h 0ff51h 8-bit timer counter 2 tm2 0ff52h compare register 10 (8-bit timer/counter 1) cr10 cr1w r/w 0ff53h compare register 20 (8-bit timer/counter 2) cr20 0ff54h 8-bit timer mode control register 1 tmc1 tmc1w 0ff55h 8-bit timer mode control register 2 tmc2 0ff56h prescaler mode register 1 prm1 prm1w 0ff57h prescaler mode register 2 prm2 0ff60h 8-bit timer counter 5 tm5 tm5w r 0ff61h 8-bit timer counter 6 tm6 0ff64h compare register 50 (8-bit timer/counter 5) cr50 cr5w r/w 0ff65h compare register 60 (8-bit timer/counter 6) cr60 0ff68h 8-bit timer mode control register 5 tmc5 tmc5w 0ff69h 8-bit timer mode control register 6 tmc6 0ff6ch prescaler mode register 5 prm5 prm5w 0ff6dh prescaler mode register 6 prm6 0ff70h asynchronous serial interface mode register 1 asim1 00h 0ff71h asynchronous serial interface mode register 2 asim2 0ff72h asynchronous serial interface status register 1 asis1 r 0ff73h asynchronous serial interface status register 2 asis2 0ff74h transmit shift register 1 txs1 w ffh receive buffer register 1 rxb1 r 0ff75h transmit shift register 2 txs2 w receive buffer register 2 rxb2 r 0ff76h baud rate generator control register 1 brgc1 r/w 00h 0ff77h baud rate generator control register 2 brgc2 0ff7ah oscillation mode select register cc 0ff80h a/d converter mode register adm 0ff81h a/d converter input select register adis 0ff83h a/d conversion result register adcr r undefined 0ff84h d/a conversion value setting register 0 dacs0 r/w 00h 0ff85h d/a conversion value setting register 1 dacs1 0ff86h d/a converter mode register 0 dam0 0ff87h d/a converter mode register 1 dam1 note when the location 0h instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 28 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 table 6-1. special function register (sfr) list (3/4) address note 1 special function register (sfr) name symbol r/w bit units for manipulation at reset 1 bit 8 bits 16 bits 0ff88h rom correction control register corc r/w 00h 0ff89h rom correction address pointer h corah 0ff8ah rom correction address pointer l coral 0000h 0ff8bh 0ff8dh external access status enable register exae 00h 0ff90h serial operation mode register 0 csim0 0ff91h serial operation mode register 1 csim1 0ff92h serial operation mode register 2 csim2 0ff94h serial i/o shift register 0 sio0 0ff95h serial i/o shift register 1 sio1 0ff96h serial i/o shift register 2 sio2 0ff98h real-time output buffer register l rtbl 0ff99h real-time output buffer register h rtbh 0ff9ah real-time output port mode register rtpm 0ff9bh real-time output port control register rtpc 0ff9ch watch timer mode control register wtm 0ffa0h external interrupt rising edge enable register egp0 0ffa2h external interrupt falling edge enable register egn0 0ffa8h in-service priority register ispr r 0ffa9h interrupt select control register snmi r/w 0ffaah interrupt mode control register imc 80h 0ffach interrupt mask flag register 0l mk0l mk0 ffffh 0ffadh interrupt mask flag register 0h mk0h 0ffaeh interrupt mask flag register 1l mk1l mk1 0ffafh interrupt mask flag register 1h mk1h 0ffb0h i 2 c bus control register note 2 iiccl0 00h 0ffb2h prescaler mode register for serial clock sprm0 0ffb4h slave address register sva0 0ffb6h i 2 c bus status register note 2 iics0 r 0ffb8h serial shift register iic0 r/w 0ffc0h standby control register stbc 30h 0ffc2h watchdog timer mode register wdm 00h 0ffc4h memory expansion mode register mm 20h 0ffc7h programmable wait control register 1 pwc1 aah 0ffc8h programmable wait control register 2 pwc2 w aaaah 00ffceh clock status register pcs r 32h 0ffcfh oscillation stabilization time specification register osts r/w 00h 0ffd0h to external sfr area 0ffdfh notes 1. when the location 0h instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. m pd784225y subseries only 29 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 table 6-1. special function register (sfr) list (4/4) address note special function register (sfr) name symbol r/w bit units for manipulation at reset 1 bit 8 bits 16 bits 0ffe0h interrupt control register (intwdtm) wdtic r/w 43h 0ffe1h interrupt control register (intp0) pic0 0ffe2h interrupt control register (intp1) pic1 0ffe3h interrupt control register (intp2) pic2 0ffe4h interrupt control register (intp3) pic3 0ffe5h interrupt control register (intp4) pic4 0ffe6h interrupt control register (intp5) pic5 0ffe8h interrupt control register (intiic0/intcsi0) csiic0 0ffe9h interrupt control register (intser1) seric1 0ffeah interrupt control register (intsr1/intcsi1) sric1 0ffebh interrupt control register (intst1) stic1 0ffech interrupt control register (intser2) seric2 0ffedh interrupt control register (intsr2/intcsi2) sric2 0ffeeh interrupt control register (intst2) stic2 0ffefh interrupt control register (inttm3) tmic3 0fff0h interrupt control register (inttm00) tmic00 0fff1h interrupt control register (inttm01) tmic01 0fff2h interrupt control register (inttm1) tmic1 0fff3h interrupt control register (inttm2) tmic2 0fff4h interrupt control register (intad) adic 0fff5h interrupt control register (inttm5) tmic5 0fff6h interrupt control register (inttm6) tmic6 0fff9h interrupt control register (intwt) wtic note when the location 0h instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 30 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 7. peripheral hardware functions 7.1 ports the ports shown in figure 7-1 are provided to make various control operations possible. table 7-1 shows the function of each port. ports 0, 2 to 7, and 12 can be connected to internal pull-up resistors by software when inputting. figure 7-1. port configuration ? port 7 ? ? ? ? ? port 0 ? ? ? ? ? port 2 ? ? ? ? ? port 3 ? ? ? ? ? port 4 port 1 p70 p72 ? ? ? ? ? port 5 p50 p57 ? ? ? ? ? port 12 p120 p127 ? port 13 p130 p131 p00 p05 p10 to p17 p20 p27 p30 p37 p40 p47 8 ? ? ? ? ? port 6 p60 p67 31 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 table 7-1. port functions port name pin name function specification of pull-up resistor connection by software port 0 p00 to p05 ? can be set in input or output mode bit-wise can be specified bit-wise port 1 p10 to p17 ? input port port 2 p20 to p27 ? can be set in input or output mode bit-wise can be specified bit-wise port 3 p30 to p37 ? can be set in input or output mode bit-wise can be specified bit-wise port 4 p40 to p47 ? can be set in input or output mode bit-wise can be specified in 1-port units ? can directly drive leds port 5 p50 to p57 ? can be set in input or output mode bit-wise can be specified in 1-port units ? can directly drive leds port 6 p60 to p67 ? can be set in input or output mode bit-wise can be specified in 1-port units port 7 p70 to p72 ? can be set in input or output mode bit-wise can be specified bit-wise port 12 p120 to p127 ? can be set in input or output mode bit-wise can be specified bit-wise port 13 p130, p131 ? can be set in input or output mode bit-wise 7.2 clock generator an on-chip clock generator necessary for operation is provided. this clock generator has a frequency divider. if high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to reduce the current consumption. figure 7-2. block diagram of clock generator xt2 xt1 x1 x2 stop and bit 2 (mck) of the standby control register (stbc) = 1 when the subsystem clock is selected as cpu clock main system clock oscillator subsystem clock oscillator f xt watch timer, clock output function clock to peripheral hardware cpu clock (f cpu ) frequency divider prescaler prescaler stop, idle controller halt controller f x f x 2 f xx 2 f xx 2 2 f xx 2 3 f xx selector selector idle controller internal system clock (f clk ) 32 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 7-3. example of using main system clock oscillator external clock x2 x1 pd74hcu04 m v ss x2 x1 crystal resorator or ceramic resonator (1) crystal/ceramic oscillation (2) external clock v ss1 figure 7-4. example of using subsystem clock oscillator 32.768 khz v ss xt2 xt1 xt2 xt1 external clock pd74hcu04 m (1) crystal oscillation (2) external clock v ss1 caution when using the main system clock and subsystem clock oscillator, wire the dotted portions in figures 7-3 and 7-4 as follows to avoid adverse influence from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring in the vicinity of lines through which a high alternating current flows. always keep the potential at the ground point of the capacitor in the oscillator the same as v ss1 . do not ground to a ground pattern through which a high current flows. do not extract signals from the oscillator. note that the subsystem clock oscillator has a low amplification factor to reduce the current consumption. 33 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 7.3 real-time output port the real-time output function is to transfer data set in advance to the real-time output buffer register to the output latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device. the pins that output the data to the external device constitute a port called a real-time output port. because the real-time output port can output signals without jitter, it is ideal for controlling a stepping motor. figure 7-5. block diagram of real-time output port internal bus rtpoe byte extr output trigger controller real-time output port control register (rtpc) real-time output port mode register (rtpm) real-time output port output latch rtp7 rtp0 higher 4 bits of real-time output buffer register (rtbh) lower 4 bits of real-time output buffer register (rtbl) intp2trg inttm1 inttm2 port 12 output latch p127 p120 p12n/rtpn pin output (n = 0 to 7) p127/ p120/ rtp7 rtp0 rtpoe bit 34 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 7.4 timer one unit of 16-bit timers/event counters, two units of timers/event counters, and two 8-bit timers are provided. because a total of six interrupt requests are supported, these timers/counters and timer can be used as six units of timers/counters. table 7-2. operations of timers name 16-bit 8-bit 8-bit 8-bit 8-bit timer/event timer/event timer/event timer 5 timer 6 item counter counter 1 counter 2 count width 8 bits 16 bits operation mode interval timer 1ch 1ch 1ch 1ch 1ch external event counter function timer output 1ch 1ch 1ch ppg output pwm output square wave output one-shot pulse output pulse width measurement 2 inputs number of interrupt requests 21111 35 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 7-6. block diagram of timers (1/2) 16-bit timer/event counter f xx /4 f xx /16 inttm3 ti01 ti00 edge detector edge detector 16-bit timer counter (tm0) 16-bit capture/compare register 00 (cr00) 16-bit capture/compare register 01 (cr01) 16 16 clear inttm00 inttm01 to0 selector selector output controller 8-bit timer/event counter 1 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 ti1 8-bit timer counter 1 (tm1) 8-bit compare register 10 (cr10) 8 clear ovf inttm2 inttm1 to1 edge detector selector selector output controller 8-bit timer/event counter 2 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 ti2 tm1 8-bit timer counter 2 (tm2) 8-bit compare register 20 (cr20) 8 clear ovf inttm2 to2 edge detector output controller selector remark ovf: overflow flag 36 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 7-6. block diagram of timers (2/2) 8-bit timer 5 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 8-bit timer counter 5 (tm5) 8-bit compare register 50 (cr50) 8 clear inttm6 inttm5 selector selector 8-bit timer 6 f xx /2 9 f xx /2 7 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 tm5 8-bit timer counter 6 (tm6) 8-bit compare register 60 (cr60) 8 clear inttm6 selector 37 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 7.5 a/d converter an a/d converter converts an analog input variable into a digital signal. this microcontroller is provided with an a/d converter with a resolution of 8 bits and 8 channels (ani0 to ani7). this a/d converter is of successive approximation type and the result of conversion is stored to an 8-bit a/d conversion result register (adcr). the a/d converter can be started in the following two ways: ? hardware start conversion is started by trigger input (p03). ? software start conversion is started by setting the a/d converter mode register. one analog input channel is selected from ani0 to ani7 for a/d conversion. when a/d conversion is started by means of hardware start, conversion is stopped after it has been completed. when conversion is started by means of software start, a/d conversion is repeatedly executed, and each time conversion has been completed, an interrupt request (intad) is generated. figure 7-7. block diagram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 sample & hold circuit series resistor string voltage comparator successive approximation register (sar) a/d conversion result register (adcr) controller edge detector intp3/p03 intad intp3 av ss av dd internal bus selector tap selector edge detector 38 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 7.6 d/a converter a d/a converter converts an input digital signal into an analog voltage. this microcontroller is provided with a voltage output type d/a converter with a resolution of 8 bits and two channels. the conversion method is of r-2r resistor ladder type. d/a conversion is started by setting dace0 of the d/a converter mode register 0 (dam0) and dace1 of the d/ a converter mode register 1 (dam1). the d/a converter operates in the following two modes: ? normal mode the converter outputs an analog voltage immediately after it has completed d/a conversion. ? real-time output mode the converter outputs an analog voltage in synchronization with an output trigger after it has completed d/a conversion. figure 7-8. block diagram of d/a converter av ref1 av ss dacs0 8 2r 2r r r 2r 2r selector ano0 dacs1 8 2r 2r r r 2r 2r selector ano1 39 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 7.7 serial interface three independent serial interface channels are provided. ? asynchronous serial interface (uart)/3-wire serial i/o (ioe) 2 ? clocked serial interface (csi) 1 ? 3-wire serial i/o (ioe) ?i 2 c bus interface (i 2 c) ( m pd784225y subseries only) therefore, communication with an external system and local communication within the system can be simultaneously executed (see figure 7-9 ). figure 7-9. example of serial interface (a) uart + i 2 c pd784225y (master) m m pd4711a m pd4711a rs-232c driver/receiver rs-232c driver/receiver [uart] [uart] ? port ? port rxd1 txd1 rxd2 txd2 sda0 scl0 [i 2 c] lcd pd780078y (slave) m pd780308y (slave) m v dd0 sda scl sda scl v dd0 (b) uart + 3-wire serial i/o pd784225y (master) pd4711a rs-232c driver/receiver [uart] ? port rxd2 txd2 pd753106 (slave) m m m si so sck port int [3-wise serial i/o] note so1 si1 sck1 intpm port note handshake line 40 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 7.7.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial i/o mode are provided. (1) asynchronous serial interface mode in this mode, data of 1 byte following the start bit is transferred or received. because an on-chip baud rate generator is provided, a wide range of baud rates can be set. moreover, the clock input to the asck pin can be divided to define a baud rate. when the baud rate generator is used, a baud rate conforming to the midi standard (31.25 kbps) can be also obtained. figure 7-10. block diagram in asynchronous serial interface mode internal bus 8 8 8 receive buffer register 1, 2 (rxb1, rxb2) receive shift register 1, 2 (rx1, rx2) transmit shift register 1, 2 (txs1, txs2) receive control parity check transmit control parity addition rxd1, rxd2 txd1, txd2 asck1, asck2 baud rate generator intsr1, intsr2 intst1, intst2 selector 5-bit counter 2 transmit/receive clock generation f xx to f xx /2 5 41 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 (2) 3-wire serial i/o mode in this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. this mode is used to communicate with a device having the conventional clocked serial interface. basically, communication is established by using three lines: serial clocks (sck1 and sck2), serial data inputs (si1 and si2), and serial data outputs (so1 and so2). to connect two or more devices, a handshake line is necessary. figure 7-11. block diagram in 3-wire serial i/o mode internal bus 8 8 direction controller interrupt generator selector serial clock counter serial clock controller serial i/o shift register 1, 2 (sio1, sio2) si1, si2 so1, so2 sck1, sck2 intcsi1, intcsi2 to2 f xx /8 f xx /16 42 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 7.7.2 clocked serial interface (csi) in this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. (1) 3-wire serial i/o mode this mode is to communicate with devices having the conventional clocked serial interface. basically, communication is established in this mode with three lines: one serial clock (sck0) and two serial data (si0 and so0) lines. generally, a handshake line is necessary to check the reception status. figure 7-12. block diagram in 3-wise serial i/o mode 8 8 si0 so0 sck0 intcsi0 to2 f xx /8 f xx /16 internal bus direction controller interrupt generator selector serial clock counter serial clock controller serial i/o shift register 0 (sio0) (2) i 2 c (inter ic) bus mode (supporting multi-master) ( m pd784225y subseries only) this mode is to communicate with devices conforming to the i 2 c bus format. this mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (scl0) and serial data bus (sda0). during transfer, a start condition, data, and stop condition can be output onto the serial data bus. during reception, these data can be automatically detected by hardware. 43 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 7-13. block diagram in i 2 c bus mode internal bus 8 8 direction controller 8 slave address register (sva0) output latch wakeup controller serial i/o shift register 0 (sio0) start condition/ acknowledge detector stop condition detector serial clock counter serial clock controller interrupt generator selector sda0 scl0 intiic0 to2/18 to to2/68 f xx /24 to f xx /178 acknowledge generator 7.8 clock output function clocks of the following frequencies can be output. ? 97.7 khz/195 khz/391 khz/781 khz/1.56 mhz/3.13 mhz/6.25 mhz/12.5 mhz (main system clock: 12.5 mhz) ? 32.768 khz (subsystem clock: 32.768 khz) figure 7-14. block diagram of clock output function f xx f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt synchronizer output controller pcl selector 44 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 7.9 buzzer output function clocks of the following frequencies can be output as buzzer output. ? 1.5 khz/3.1 khz/6.1 khz/12.2 khz (main system clock: 12.5 mhz) figure 7-15. block diagram of buzzer output function f xx /2 10 f xx /2 11 f xx /2 12 f xx /2 13 output controller buz selector 7.10 edge detection function the interrupt input pins (intp0, intp1, nmi/intp2, intp3 to intp5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. because these pins operate at an edge of the input signal, they have a function to detect an edge. moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise. pin name detectable edge noise reduction nmi either or both of rising and falling edges by analog delay intp0 to intp5 7.11 watch timer the watch timer has the following functions: ? watch timer ? interval timer the watch timer and interval timer functions can be used at the same time. (1) watch timer the watch timer sets the wtif flag of the interrupt control register (wtic) at time intervals of 0.5 seconds by using the 32.768-khz subsystem clock. (2) interval timer the interval timer generates an interrupt request (inttm3) at predetermined time intervals. 45 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 7-16. block diagram of watch timer f xx /2 7 prescaler f xt f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w f w 2 9 5-bit counter f w 2 5 f w 2 14 intwt inttm3 to 16-bit timer/counter selector selector selector selector 7.12 watchdog timer a watchdog timer is provided to detect a hang up of the cpu. this watchdog timer generates a non-maskable or maskable interrupt unless it is cleared by software within a specified interval time. once enabled to operate, the watchdog timer cannot be stopped by software. whether the interrupt by the watchdog timer or the interrupt input from the nmi pin takes precedence can be specified. figure 7-17. block diagram of watchdog timer selector f clk /2 21 f clk /2 20 f clk /2 19 f clk /2 17 f clk timer intwdt run note halt idle stop note write 1 to bit 7 (run) of the watchdog timer (wdm). remark f clk : internal system clock (f xx to f xx /8) 46 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 8. interrupt function as the servicing in response to an interrupt request, the three types shown in table 8-1 can be selected by program. table 8-1. servicing of interrupt request servicing mode entity of servicing servicing contents of pc and psw vectored interrupt software branches and executes servicing routine saves to and restores (servicing is arbitrary). from stack. context switching automatically switches register bank, saves to or restores from branches and executes servicing routine fixed area in register bank (servicing is arbitrary). macro service firmware executes data transfer between memory retained and i/o (servicing is fixed) 8.1 interrupt sources table 8-2 shows the interrupt sources available. as shown, interrupts are generated by 25 types of sources, execution of the brk instruction, brkcs instruction, or an operand error. the priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. when the macro service function is used, however, nesting always proceeds. the default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same request, simultaneously generate (see table 8-2 ). 47 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 table 8-2. interrupt sources type default source internal/ macro priority name trigger external service software brk instruction instruction execution brkcs instruction instruction execution operand error if result of exclusive or between operands byte and byte is not ffh when mov stbc, #byte instruction or mov wdm, #byte instruction, location instruction is executed non-maskable nmi pin input edge detection external intwdt overflow of watchdog timer internal maskable 0 ( highest ) intwdtm overflow of watchdog timer internal 1 intp0 pin input edge detection external 2 intp1 3 intp2 4 intp3 5 intp4 6 intp5 7 intiic0 note end of i 2 c bus transfer by csi0 internal intcsi0 end of 3-wire transfer by csi0 8 intser1 occurrence of uart reception error in asi1 9 intsr1 end of uart reception by asi1 intcsi1 end of 3-wire transfer by csi1 10 intst1 end of uart transfer by asi1 11 intser2 occurrence of uart reception error in asi2 12 intsr2 end of uart reception by asi2 intcsi2 end of 3-wire transfer by csi2 13 intst2 end of uart transfer by asi2 14 inttm3 reference time interval signal from watch timer 15 inttm00 signal indicating coincidence between 16-bit timer counter and capture/compare register (cr00) 16 inttm01 signal indicating coincidence between 16-bit timer counter and capture/compare register (cr01) 17 inttm1 occurrence of coincidence signal of 8-bit timer/counter 1 18 inttm2 occurrence of coincidence signal of 8-bit timer/counter 2 19 intad end of conversion by a/d converter 20 inttm5 occurrence of coincidence signal of 8-bit timer/counter 5 21 inttm6 occurrence of coincidence signal of 8-bit timer/counter 6 22 (lowest) intwt overflow of watch timer note m pd784255y subseries only remarks 1. asi : asynchronous serial interface csi : clocked serial interface 2. there are two interrupt sources for the watchdog timer: non-maskable interrupts (intwdt) and maskable interrupts (intwdtm). either one (but not both) should be selected for actual use. 48 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 8.2 vectored interrupt execution branches to a servicing routing by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. so that the cpu performs interrupt servicing, the following operations are performed: ? on branching: saves the status of the cpu (contents of pc and psw) to stack ? on returning : restores the status of the cpu (contents of pc and psw) from stack to return to the main routine from an interrupt service routine, the reti instruction is used. the branch destination address is in a range of 0 to ffffh. table 8-3. vector table address interrupt source vector table address interrupt source vector table address brk instruction 003eh intst1 001ch operand error 003ch intser2 001eh nmi 0002h insr2 0020h intwdt ( non-maskable ) 0004h intcsi2 intwdtm (maskable) 0006h intst2 0022h intp0 0008h inttm3 0024h intp1 000ah inttm00 0026h intp2 000ch inttm01 0028h intp3 000eh inttm1 002ah intp4 0010h inttm2 002ch intp5 0012h intad 002eh intiic0 0016h inttm5 00030h intcsi0 inttm6 0032h intser1 0018h intwt 0038h intsr1 001ah intcsi1 49 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 8.3 context switching when an interrupt request is generated or when the brkcs instruction is executed, a predetermined register bank is selected by hardware. context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (pc) and program status word (psw) to the register bank. the branch address is in a range of 0 to ffffh. figure 8-1. context switching operation when interrupt request is generated register bank n (n = 0 to 7) 0000b <7> transfer pc19 to pc16 pc15 to pc0 <6> exchange <5> save <2> save temporary register <1> save psw v u t w a b r5 r7 d h x c r4 r6 e l vp up <3> switching of register bank (rbs0 to rbs2 ? n) register bank n (0 to 7) (bits 8 through 11 of temporary register) <4> rss ? 0 ie ? 0 8.4 macro service this function is to transfer data between memory and a special function register (sfr) without intervention by the cpu. a macro service controller accesses the memory and sfr in the same transfer cycle and directly transfers data without loading it. because this function does not save or restore the status of the cpu, or load data, data can be transferred at high speeds. figure 8-2. macro service cpu memory sfr macro service controller read write write read internal bus 50 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 8.5 application example of macro service (1) transmission of serial interface transfer data storage buffer (memory) data n data n - 1 data 1 data 2 internal bus transmit shift register txs1, txs2 (sfr) transfer control txd1, txd2 intst1, intst2 each time macro service request intst1 and intst2 are generated, the next transmit data is transferred from memory to txs1 and txs2. when data n (last byte) has been transferred to txs1 and txs2 (when the transmit data storage buffer has become empty), vectored interrupt request intst1 and intst2 are generated. (2) reception of serial interface receive data storage buffer (memory) data n data n - 1 data 1 data 2 internal bus receive shift register rxb1, rxb2 (sfr) reception control intsr1, intsr2 rxd1, rxd2 receive buffer register each time macro service request intsr1 and intsr2 are generated, the receive data is transferred from rxb1 and rxb2 to memory. when data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request intsr1 and intsr2 are generated. 51 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 9. local bus interface the local bus interface can connect an external memory or i/o (memory mapped i/o) and support a memory space of 1 mbyte (refer to figure 9-1 ). figure 9-1. example of local bus interface (multiplexed bus) m pd784225 rd wr a8 to a19 astb ad0 to ad7 v dd1 address latch le q0 to q7 d0 to d7 oe sram cs oe we i/o1 to i/o8 a0 to a19 data bus address bus 9.1 memory expansion external program and data memory can be connected in two stages: 256 kbytes and 1 mbytes. to connect the external memory, ports 4 to 6 are used. the external memory is connected by using a time-division address/data bus. the number of ports used when the external memory is connected can be reduced in this mode. 9.2 programmable wait wait state(s) can be inserted to the memory space (00000h to fffffh) while the rd and wr signals are active. in addition, there is an address wait function that extends the active period of the astb signal to gain the address decode time. 9.3 external access status function an active low external access status signal is output from the p37/exa pin. this signal notifies other devices connected to the external bus of the external access status, to disable data output to the external bus from other devices, or enables reception. the external access status signal is output during external access. 52 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 10. standby function this function is to reduce the power consumption of the chip, and can be used in the following modes: ? halt mode : stops supply of the operating clock to the cpu. this mode is used in combination with the normal operation mode for intermittent operation to reduce the average power consumption. ? idle mode : stops the entire system with the oscillator continuing operation. the power consumption in this mode is close to that in the stop mode. however, the time required to restore the normal program operation from this mode is almost the same as that from the halt mode. ? stop mode : stops the main system clock and thereby to stop all the internal operations of the chip. consequently, the power consumption is minimized with only leakage current flowing. ? power-saving mode : the main system clock is stopped with the subsystem clock used as the system clock. the cpu can operate on the subsystem clock to reduce the current consumption. ? power-saving halt mode : this is a standby function in the power-saving mode and stops the operation clock of the cpu, to reduce the power consumption of the entire system. ? power-saving idle mode : this is a standby function in the power-saving mode and stops the entire system except the oscillator, to reduce the power consumption of the entire system. these modes are programmable. the macro service can be started from the halt mode and power-saving halt mode. after executing macro service processing, it returns to the halt mode. 53 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 figure 10-1. transition of standby status waits for oscillation stabilization normal operation (operation on main system clock) macro service halt (standby) idle (standby) power- saving mode (operation on subsystem clock) power- saving halt mode (standby) power- saving idle mode (standby) stop (standby) end of oscillation stabilization time macro service request end of one processing end of macro service macro service request end of one processing interrupt request reset input sets halt mode sets idle mode reset input nmi, intp0 to intp6 input, intwt, key return interrupt note 2 nmi, intp0 to intp6 input, intwt, key return interrupt note 2 sets stop mode power-saving idle mode is set. reset input power-saving halt mode is set. normal operation is restored. nmi, intp0 to intp6 input, intwt note 2 power-saving halt mode is set. reset input interrupt request note 1 interrupt request of masked interrupt interrupt request of masked interrupt interrupt request of masked interrupt interrupt request of masked interrupt interrupt request of masked interrupt reset input reset input macro service macro service request macro service request end of one processing end of macro service end of one processing notes 1. only unmasked interrupt requests 2. only unmasked intp0 to intp6, intwt, key return interrupt (p80 to p87) remark nmi is valid only for an external input. the watchdog timer cannot be used for the release of standby (halt mode/stop mode/idle mode). 54 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 11. reset function when a low-level signal is input to the reset pin, the system is reset, and each hardware unit is initialized (reset). during the reset period, oscillation of the main system clock is unconditionally stopped. consequently, the current consumption of the entire system can be reduced. when the reset signal goes high, the reset status is cleared, oscillation stabilization time (41.9 ms at 12.5 mhz) elapses, the contents of the reset vector table are set to the program counter (pc), execution branches to an address set to the pc, and program execution is started from that branch address. therefore, the program can be reset and started from any address. figure 11-1. oscillation of main system clock during reset period oscillation is unconditionally stopped during rest period oscillation stabilization time main system clock oscillator f clk reset input the reset input pin has an analog delay noise eliminator to prevent malfunctioning due to noise. figure 11-2. accepting reset signal analog delay analog delay analog delay oscillation stabilization time reset input internal reset signal internal clock time until the clock starts oscillation 55 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 12. rom correction rom correction is a function to replace part of the program in the internal rom with a program in the internal ram. by using the rom correction function, instruction bugs found in the internal rom can be avoided or the flow of the program can be changed. rom correction can be used at up to four places in the internal rom (program). figure 12-1. block diagram of rom correction corenn corchm program counter (pc) comparator correction address pointer n correction address registers (corah, coral) coincidence correction branch processing request signal (callt instruction) internal bus rom correction control register (corc) remark n = 0 to 3, m = 0 or 1 56 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 13. instruction set (1) 8-bit instructions (the instructions in parentheses are combinations realized by describing a as r) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chkl, chkla table 13-1. instruction list by 8-bit addressing second operand #byte a r saddr sfr !addr16 mem r3 [whl+] n none note 2 r' saddr' !!addr24 [saddrp] pswl [whlC] first operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) note 1,6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop chkl chkla !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 [tdeC] (add) note 1 movm note 4 notes 1. the operands of addc, sub, subc, and, or, xor, and cmp are the same as that of add. 2. either the second operand is not used, or the second operand is not an operand address. 3. the operands of rol, rorc, rolc, shr, and shl are the same as that of ror. 4. the operands of xchm, cmpme, cmpmne, cmpmnc, and cmpmc are the same as that of movm. 5. the operands of xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are the same as that of movbk. 6. the code length of some instructions having saddr2 as saddr in this combination is short. 57 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 (2) 16-bit instructions (the instructions in parentheses are combinations realized by describing ax as rp) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 13-2. instruction list by 16-bit addressing second operand #word ax rp saddrp sfrp !addr16 mem [whl+] byte n none note 2 rp' saddrp' !!addr24 [saddrp] first operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (add) note 1 (addw) note 1 (addw) note 1,3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw notes 1. the operands of subw and cmpw are the same as that of addw. 2. either the second operand is not used, or the second operand is not an operand address. 3. the code length of some instructions having saddrp2 as saddrp in this combination is short. 4. the operands of muluw and divux are the same as that of mulw. 58 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 (3) 24-bit instructions (the instructions in parentheses are combinations realized by describing whl as rg) movg, addg, subg, incg, decg, push, pop table 13-3. instruction list by 24-bit addressing second operand #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note rg' first operand whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note either the second operand is not used, or the second operand is not an operand address. 59 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 13-4. bit manipulation instructions second operand cy saddr.bit sfr.bit /saddr.bit /sfr. bit none note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit first operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note either the second operand is not used, or the second operand is not an operand address. 60 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 (5) call and return/branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 13-5. call and return/branch instructions operand of instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none address basic instruction bc note call call call call call call call callf callf brkcs brk br br br br br br br br ret retcs reti retcsb retb compound instruction bf bt btclr bfset dbnz note the operands of bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs 61 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 14. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd0 - 0.3 to +6.5 v av dd - 0.3 to v dd0 + 0.3 v av ss - 0.3 to v ss0 + 0.3 v av ref1 d/a converter reference voltage input - 0.3 to v dd0 + 0.3 v input voltage v i - 0.3 to v dd0 + 0.3 v analog input voltage v an analog input pin av ss - 0.3 to av ref1 + 0.3 v output voltage v o - 0.3 to v dd + 0.3 v output current, low i ol per pin 15 ma total of all pins 100 ma output current, high i oh per pin - 10 ma total of all pins - 40 ma operating ambient t a - 40 to +85 c temperature storage temperature t stg - 65 to +150 c caution absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. always use the product within its rated values. 62 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 operating conditions operating ambient temperature (t a ): - 40 c to +85 c power supply voltage and clock cycle time: see figure 14-1 operating voltage when the subsystem clock is operating: v dd = 1.8 to 5.5 v figure 14-1. power supply voltage and clock cycle time (cpu clock frequency: f cpu ) 8,000 10,000 500 400 300 320 160 80 200 100 0 0123 1.8 2.7 4.5 5.5 supply voltage [v] 456 clock cycle time t cyk [ns] guaranteed operation range capacitance (t a = 25 c, v dd = v dd0 = v dd1 = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 15 pf output capacitance c o unmeasured pins returned to 0 v. 15 pf i/o capacitance c io 15 pf 63 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 main system clock oscillator characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 ) resonator recommended circuit parameter conditions min. typ. max. unit ceramic oscillation frequency (f x ) 4.5 v v dd 5.5 v 2 12.5 mhz resonator 2.7 v v dd < 4.5 v 2 6.25 or crystal 2.0 v v dd < 2.7 v 2 3.125 resonator 1.8 v v dd < 2.0 v 2 2 external x1 input frequency (f x ) 4.5 v v dd 5.5 v 2 12.5 mhz clock 2.7 v v dd < 4.5 v 2 6.25 2.0 v v dd < 2.7 v 2 3.125 1.8 v v dd < 2.0 v 2 2 x1 input high-/low- 15 250 ns level width (t wxh , t wxl ) x1 input rising/falling 4.5 v v dd 5.5 v 0 5 ns time (t xr , t xf ) 2.7 v v dd < 4.5 v 0 10 2.0 v v dd < 2.7 v 0 20 1.8 v v dd < 2.0 v 0 30 cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. x2 x1 v ss x2 x1 pd74hcu04 m 64 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 subsystem clock oscillator characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 ) resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillation frequency (f xt )32 32.768 35 khz resonator oscillation stabilization 4.5 v v dd 5.5 v 1.2 2 s time note 1.8 v v dd < 4.5 v 10 external xt1 input frequency (f xt ) 32 35 khz clock xt1 input high-/low-level 14.3 15.6 m s width (t xth , t xtl ) note time required to stabilize oscillation after applying supply voltage (v dd ). cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. v ss xt2 xt1 xt2 xt1 pd74hcu04 m 65 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 dc characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit input voltage, low v il1 note 1 2.2 v v dd 5.5 v 0 0.3v dd v 1.8 v v dd < 2.2 v 0 0.2v dd v il2 p00 to p05, p20, p22, p33, 2.2 v v dd 5.5 v 0 0.2v dd v p34, p70, p72, reset 1.8 v v dd < 2.2 v 0 0.15v dd v il4 p10 to p17, p130, p131 2.2 v v dd 5.5 v 0 0.3v dd v 1.8 v v dd < 2.2 v 0 0.2v dd v il5 x1, x2, xt1, xt2 2.2 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 2.2 v 0 0.1v dd v il6 p25, p27 2.2 v v dd 5.5 v 0 0.3v dd v 1.8 v v dd < 2.2 v 0 0.2v dd input voltage, high v ih1 note 1 2.2 v v dd 5.5 v 0.7v dd v dd v 1.8 v v dd < 2.2 v 0.8v dd v dd v ih2 p00 to p05, p20, p22, p33, 2.2 v v dd 5.5 v 0.8v dd v dd v p34, p70, p72, reset 1.8 v v dd < 2.2 v 0.85v dd v dd v ih4 p10 to p17, p130, p131 2.2 v v dd 5.5 v 0.7v dd v dd v 1.8 v v dd < 2.2 v 0.8v dd v dd v ih5 x1, x2, xt1, xt2 2.2 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 2.2 v 0.85v dd v dd v ih6 p25, p27 2.2 v v dd 5.5 v 0.7v dd v dd v 1.8 v v dd < 2.2 v 0.8v dd v dd output voltage, low v ol1 for pins other than 4.5 v v dd 5.5 v 0.4 v p40 to p47, p50 to p57, i ol = 1.6 ma note 2 p40 to p47, p50 to p57 4.5 v v dd 5.5 v 1.0 v i ol = 8 ma note 2 v ol2 i ol = 400 m a note 2 0.5 v output voltage, high v oh1 i oh = - 1 ma note 2 4.5 v v dd 5.5 v v dd - 1.0 v i oh = - 100 m a note 2 v dd - 0.5 v input leakage current, i lil1 v in = 0 v except x1, x2, - 3 m a low xt1, xt2 i lil2 x1, x2, xt1, xt2 - 20 m a input leakage current, i lih1 v in = v dd0 except x1, x2, 3 m a high xt1, xt2 i lih2 x1, x2, xt1, xt2 20 m a output leakage current, i lol1 v out = 0 v - 3 m a low output leakage current, i loh1 v out = v dd 3 m a high notes 1. p21, p23, p24, p26, p30 to p32, p35 to p37, p40 to p47, p50 to p57, p60 to p67, p71, p80 to p87, p120 to p127 2. per pin 66 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 dc characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit supply voltage i dd1 operation f xx = 12.5 mhz, v dd = 5.0 v 10% 17 40 ma mode f xx = 6 mhz, v dd = 3.0 v 10% 5 17 ma f xx = 2 mhz, v dd = 2.0 v 10% 2 8 ma i dd2 halt mode f xx = 12.5 mhz, v dd = 5.0 v 10% 7 20 ma f xx = 6 mhz, v dd = 3.0 v 10% 2 8 ma f xx = 2 mhz, v dd = 2.0 v 10% 0.5 3.5 ma i dd3 idle mode f xx = 12.5 mhz, v dd = 5.0 v 10% 1 2.5 ma f xx = 6 mhz, v dd = 3.0 v 10% 0.4 1.3 ma f xx = 2 mhz, v dd = 2.0 v 10% 0.2 0.9 ma i dd4 operation f xx = 32 khz, v dd = 5.0 v 10% 80 200 m a mode note f xx = 32 khz, v dd = 3.0 v 10% 60 110 m a f xx = 32 khz, v dd = 2.0 v 10% 30 100 m a i dd5 halt f xx = 32 khz, v dd = 5.0 v 10% 60 160 m a mode note f xx = 32 khz, v dd = 3.0 v 10% 20 80 m a f xx = 32 khz, v dd = 2.0 v 10% 10 70 m a i dd6 idle f xx = 32 khz, v dd = 5.0 v 10% 50 150 m a mode note f xx = 32 khz, v dd = 3.0 v 10% 15 70 m a f xx = 32 khz, v dd = 2.0 v 10% 5 60 m a data retention voltage v dddr halt, idle modes 1.8 5.5 v data retention current i dddr stop mode v dd = 2.0 v 10% 2 10 m a v dd = 5.0 v 10% 10 50 m a pull-up resistor r l v in = 0 v 10 30 100 k w note when main system clock is stopped. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 67 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 ac characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) (1) read/write operation (1/3) parameter symbol conditions min. typ. max. unit cycle time t cyk 4.5 v v dd 5.5 v 80 ns 2.7 v v dd < 4.5 v 160 ns 2.0 v v dd < 2.7 v 320 ns 1.8 v v dd < 2.0 v 500 ns address setup time t sast v dd = 5.0 v 10% (0.5 + a) t - 20 ns (to astb ) v dd = 3.0 v 10% (0.5 + a) t - 40 ns v dd = 2.0 v 10% (0.5 + a) t - 80 ns address hold time t hstla v dd = 5.0 v 10% 0.5t - 19 ns (from astb ) v dd = 3.0 v 10% 0.5t - 24 ns v dd = 2.0 v 10% 0.5t - 34 ns astb high-level width t wsth v dd = 5.0 v 10% (0.5 + a) t - 17 ns v dd = 3.0 v 10% (0.5 + a) t - 40 ns v dd = 2.0 v 10% (0.5 + a) t - 110 ns address hold time t hra v dd = 5.0 v 10% 0.5t - 14 ns (from rd - ) v dd = 3.0 v 10% 0.5t - 14 ns v dd = 2.0 v 10% 0.5t - 14 ns delay time from address to t dar v dd = 5.0 v 10% (1 + a) t - 24 ns rd v dd = 3.0 v 10% (1 + a) t - 35 ns v dd = 2.0 v 10% (1 + a) t - 80 ns address float time t far v dd = 5.0 v 10% 0 ns (from rd ) v dd = 3.0 v 10% 0 ns v dd = 2.0 v 10% 0 ns data input time from t daid v dd = 5.0 v 10% (2.5 + a + n) t - 37 ns address v dd = 3.0 v 10% (2.5 + a + n) t - 52 ns v dd = 2.0 v 10% (2.5 + a + n) t - 120 ns data input time from astb t dstid v dd = 5.0 v 10% (2 + n) t - 35 ns v dd = 3.0 v 10% (2 + n) t - 50 ns v dd = 2.0 v 10% (2 + n) t - 80 ns data input time from rd t drid v dd = 5.0 v 10% (1.5 + n) t - 40 ns v dd = 3.0 v 10% (1.5 + n) t - 50 ns v dd = 2.0 v 10% (1.5 + n) t - 90 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 3 0) 68 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 ac characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) (1) read/write operation (2/3) parameter symbol conditions min. typ. max. unit delay time from astb t dstr v dd = 5.0 v 10% 0.5t - 9ns to rd v dd = 3.0 v 10% 0.5t - 9ns v dd = 2.0 v 10% 0.5t - 20 ns data hold time (from rd - )t hrid v dd = 5.0 v 10% 0 ns v dd = 3.0 v 10% 0 ns v dd = 2.0 v 10% 0 ns address active time from t dra v dd = 5.0 v 10% 0.5t - 2ns rd - v dd = 3.0 v 10% 0.5t - 12 ns v dd = 2.0 v 10% 0.5t - 35 ns delay time from rd - to t drst v dd = 5.0 v 10% 0.5t - 9ns astb - v dd = 3.0 v 10% 0.5t - 9ns v dd = 2.0 v 10% 0.5t - 40 ns rd low-level width t wrl v dd = 5.0 v 10% (1.5 + n) t - 25 ns v dd = 3.0 v 10% (1.5 + n) t - 30 ns v dd = 2.0 v 10% (1.5 + n) t - 25 ns delay time from address to t daw v dd = 5.0 v 10% (1 + a) t - 24 ns wr v dd = 3.0 v 10% (1 + a) t - 34 ns v dd = 2.0 v 10% (1 + a) t - 70 ns address hold time t hrd v dd = 5.0 v 10% 0.5t - 14 ns (from wr - ) v dd = 3.0 v 10% 0.5t - 14 ns v dd = 2.0 v 10% 0.5t - 14 ns delay time from astb to t dstod v dd = 5.0 v 10% 0.5t + 15 ns data output v dd = 3.0 v 10% 0.5t + 30 ns v dd = 2.0 v 10% 0.5t + 240 ns delay time from wr to t dwod v dd = 5.0 v 10% 0.5t - 30 ns data output v dd = 3.0 v 10% 0.5t - 30 ns v dd = 2.0 v 10% 0.5t - 30 ns delay time from astb to t dstw v dd = 5.0 v 10% 0.5t - 9ns wr v dd = 3.0 v 10% 0.5t - 9ns v dd = 2.0 v 10% 0.5t - 20 ns data setup time (to wr - )t sodwr v dd = 5.0 v 10% (1.5 + n) t - 20 ns v dd = 3.0 v 10% (1.5 + n) t - 25 ns v dd = 2.0 v 10% (1.5 + n) t - 70 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 3 0) 69 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 ac characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) (1) read/write operation (3/3) parameter symbol conditions min. typ. max. unit data hold time (from wr - )t hwod v dd = 5.0 v 10% 0.5t - 14 ns v dd = 3.0 v 10% 0.5t - 14 ns v dd = 2.0 v 10% 0.5t - 50 ns delay time from wr - to t dwst v dd = 5.0 v 10% 0.5t - 9ns astb - v dd = 3.0 v 10% 0.5t - 9ns v dd = 2.0 v 10% 0.5t - 30 ns wr low-level width t wwl v dd = 5.0 v 10% (1.5 + n) t - 25 ns v dd = 3.0 v 10% (1.5 + n) t - 30 ns v dd = 2.0 v 10% (1.5 + n) t - 30 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 3 0) 70 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 ac characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) (2) external wait timing (1/2) parameter symbol conditions min. typ. max. unit input time from address to t dawt v dd = 5.0 v 10% (2 + a) t - 40 ns wait v dd = 3.0 v 10% (2 + a) t - 60 ns v dd = 2.0 v 10% (2 + a) t - 300 ns input time from astb to t dstwt v dd = 5.0 v 10% 1.5t - 40 ns wait v dd = 3.0 v 10% 1.5t - 60 ns v dd = 2.0 v 10% 1.5t - 260 ns hold time from astb to t hstwt v dd = 5.0 v 10% (0.5 + n) t + 5 ns wait v dd = 3.0 v 10% (0.5 + n) t + 10 ns v dd = 2.0 v 10% (0.5 + n) t + 30 ns delay time from astb to t dstwth v dd = 5.0 v 10% (1.5 + n) t - 40 ns wait - v dd = 3.0 v 10% (1.5 + n) t - 60 ns v dd = 2.0 v 10% (1.5 + n) t - 90 ns input time from rd to t drwtl v dd = 5.0 v 10% t - 40 ns wait v dd = 3.0 v 10% t - 60 ns v dd = 2.0 v 10% t - 70 ns hold time from rd to t hrwt v dd = 5.0 v 10% nt + 5 ns wait v dd = 3.0 v 10% nt + 10 ns v dd = 2.0 v 10% nt + 30 ns delay time from rd to t drwth v dd = 5.0 v 10% (1 + n) t - 40 ns wait - v dd = 3.0 v 10% (1 + n) t - 60 ns v dd = 2.0 v 10% (1 + n) t - 90 ns input time from wait - to t dwtid v dd = 5.0 v 10% 0.5t - 5ns data v dd = 3.0 v 10% 0.5t - 10 ns v dd = 2.0 v 10% 0.5t - 30 ns delay time from wait - to t dwtr v dd = 5.0 v 10% 0.5t ns rd - v dd = 3.0 v 10% 0.5t ns v dd = 2.0 v 10% 0.5t + 5 ns delay time from wait - to t dwtw v dd = 5.0 v 10% 0.5t ns wr - v dd = 3.0 v 10% 0.5t ns v dd = 2.0 v 10% 0.5t + 5 ns delay time from wr to t dwwtl v dd = 5.0 v 10% t - 40 ns wait v dd = 3.0 v 10% t - 60 ns v dd = 2.0 v 10% t - 90 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 3 0) 71 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 (2) external wait timing (2/2) parameter symbol conditions min. typ. max. unit hold time from wr to t hwwt v dd = 5.0 v 10% nt + 5 ns wait v dd = 3.0 v 10% nt + 10 ns v dd = 2.0 v 10% nt + 30 ns delay time from wr to t dwwth v dd = 5.0 v 10% (1 + n) t - 40 ns wait - v dd = 3.0 v 10% (1 + n) t - 60 ns v dd = 2.0 v 10% (1 + n) t - 90 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 3 0) 72 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 serial operation (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) (a) 3-wire serial i/o mode (sck: internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 2.7 v v dd 5.5 v 800 ns 3,200 ns sck high-/low-level t kh1 , 2.7 v v dd 5.5 v 350 ns width t kl1 1,500 ns si setup time (to sck - )t sik1 2.7 v v dd 5.5 v 10 ns 30 ns si hold time (from sck - ) t ksi1 40 ns so output delay time t kso1 30 ns (from sck ) (b) 3-wire serial i/o mode (sck: external clock input) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 2.7 v v dd 5.5 v 800 ns 3,200 ns sck high-/low-level t kh2 2.7 v v dd 5.5 v 400 ns width t kl2 1,600 ns si setup time (to sck - )t sik2 2.7 v v dd 5.5 v 10 ns 30 ns si hold time (from sck - ) t ksi2 40 ns so output delay time t kso2 30 ns (from sck ) (c) uart mode parameter symbol conditions min. typ. max. unit asck cycle time t kcy3 4.5 v v dd 5.5 v 417 ns 2.7 v v dd < 4.5 v 833 ns 1,667 ns asck high-/low-level t kh3 4.5 v v dd 5.5 v 208 ns width t kl3 2.7 v v dd < 4.5 v 416 ns 833 ns 73 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 (d) i 2 c bus mode ( m pd784225y only) parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 khz bus free time (between stop t buf 4.7 - 1.3 - m s and start conditions) hold time note1 t hd : sta 4.0 - 0.6 - m s low-level width of scl0 t low 4.7 - 1.3 - m s clock high-level width of scl0 t high 4.0 - 0.6 - m s clock setup time of start/restart t su : sta 4.7 - 0.6 - m s conditions data hold when using t hd : dat 5.0 --- m s time cbus-compatible master when using i 2 c0 note 2 - 0 note 2 0.9 note 3 m s bus data setup time t su : dat 250 - 100 note 4 - ns rising time of sda0 and t r - 1,000 20 + 0.1cb note 5 300 ns scl0 signals falling time of sda0 and t f - 300 20 + 0.1cb note 5 300 ns scl0 signals setup time of stop condition t su : sto 4.0 - 0.6 - m s pulse width of spike t sp -- 050ns restricted by input filter load capacitance of each cb - 400 - 400 pf bus line notes 1. for the start condition, the first clock pulse is generated after the hold time. 2. to fill the undefined area of the scl0 falling edge, it is necessary for the device to provide an internal sda0 signal (on v ihmin. ) with at least 300 ns of hold time. 3. if the device does not extend the scl0 signal low-level hold time (t low ), only the maximum data hold time t hd : dat needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in a standard mode i 2 c bus system. in this case, the conditions described below must be satisfied. if the device does not extend the scl0 signal low-level hold time t su : dat 3 250 ns if the device extends the scl0 signal low-level hold time be sure to transmit the data bit to the sda0 line before the scl0 line is released (t rmax. + t su : dat = 1,000 + 250 = 1,250 ns by standard mode i 2 c bus specification) 5. cb: total capacitance per bus line (unit: pf) 74 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 other operations (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) parameter symbol conditions min. typ. max. unit nmi high-/low-level t wnil 10 m s width t wnih intp input high-/low- t witl intp0 to intp6 100 ns level width t with reset high-/low-level t wrsl 10 m s width t wrsh clock output operation (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) parameter symbol conditions min. typ. max. unit pcl cycle time t cycl 4.5 v v dd 5.5 v, nt 80 31,250 ns pcl high-/low-level t cll 4.5 v v dd 5.5 v, 0.5t - 10 30 15,615 ns width t clh pcl rising/falling time t clr 4.5 v v dd 5.5 v 5 ns t clf 2.7 v v dd < 4.5 v 10 ns 1.8 v v dd < 2.7 v 20 ns remark t: t cyk = 1/f xx (f xx : main system clock frequency) n: divided frequency ratio set by software in the cpu when using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128 when using the subsystem clock: n = 1 75 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 a/d converter characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit overall error note 6.25 mhz < f xx 12.5 mhz, 1.2 %fsr 4.5 v v dd 5.5 v, av dd = v dd0 3.125 mhz < f xx 6.25 mhz, 1.2 %fsr 2.7 v v dd 5.5 v, av dd = v dd0 2 mhz < f xx 3.125 mhz, 1.6 %fsr 2.0 v v dd 5.5 v, av dd = v dd0 f xx = 2 mhz, 1.8 v v dd 5.5 v 1.6 %fsr av dd = v dd0 conversion time t conv 14 144 m s sampling time t samp 24/f xx m s analog input voltage v ian av ss av dd v reference voltage av dd v dd v dd v dd v resistance between r avref0 a/d conversion is not performed 40 k w av dd and av ss note excludes quantization error ( 0.2%fsr). remark fsr: full-scale range d/a converter characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit overall error note 2.0 v v dd 5.5 v 0.6 %fsr r = 10 m w , 2.0 v av ref1 5.5 v 1.8 v v dd 2.0 v 1.2 %fsr r = 10 m w , 1.8 v av ref1 5.5 v settling time load conditions: 4.5 v av ref1 5.5 v 10 m s c = 30 pf 2.7 v av ref1 < 4.5 v 15 m s 1.8 v av ref1 < 2.7 v 20 m s output resistance r o dacs0, 1 = 55h 8 k w reference voltage av ref1 1.8 v dd0 v av ref1 current ai ref1 for only 1 channel 2.5 ma note excludes quantization error ( 0.2%fsr). remark fsr: full-scale range 76 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 data retention characteristics (t a = - 40 c to +85 c, v dd = v dd0 = v dd1 = av dd = 1.8 to 5.5 v, v ss = v ss0 = v ss1 = av ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 1.8 5.5 v data retention current i dddr v dddr = 5.0 v 10% 10 50 m a v dddr = 2.0 v 10% 2 10 m a v dd rise time t rvd 200 m s v dd fall time t fvd 200 m s v dd hold time (from t hvd 0ms stop mode setting) stop release signal t drel 0ms input time oscillation stabilization t wait crystal resonator 30 ms wait time ceramic resonator 5 ms low-level input voltage v il reset, p00/intp0 to p06/intp6 0 0.1v dddr v high-level input voltage v ih 0.9v dddr v dddr v ac timing measurement points 0.8v dd or 1.8 v 0.8 v 0.8v dd or 1.8 v 0.8 v points of measurement v dd - 1 v 0.45 v 77 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 timing waveform (1) read operation (clk) a8 to a19 (output) astb (output) rd (output) wait (input) ad0 to ad7 (input/output) t cyk higher address hi-z hi-z hi-z higher address a0 to a7 (output) lower address lower address data (input) lower address (output) lower address (output) t daid t hra t sast t wsth t dstr t drst t dar t drid t wrl t drwth t dstwt t dstwth t hstwt t hrwt t dawt t dwtr t hstla t far t dwtid t drwtl t hrid t dra t dstid 78 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 (2) write operation (clk) a8 to a19 (output) astb (output) wait (input) ad0 to ad7 (output) t cyk t daid t hwa t sast t wsth t dstw t dwst t daw t dwod t wwl t dwwth t dstwt t dstwth t hstwt t hwwt t dawt t dwtw t hstla t far t dwtid t dwwtl t hwod t daw t dstod t sodwr hi-z hi-z hi-z wr (output) higher address higher address a0 to a7 (output) lower address lower address data (output) lower address (output) lower address (output) 79 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 serial operation (1) 3-wire serial i/o mode sck si/so t kcy1, 2 t kl1, 2 t kh1, 2 t kso1, 2 t sik1, 2 t ksi1, 2 (2) uart mode asck t kcy3 t kh3 t kl3 (3) i 2 c bus mode ( m pd784255y subseries only) scl0 sda0 t r t hd : dat t hd : sta t buf t high t su : dat t f t su : sta t hd : sta t sp t su : sto stop condition start condition restart condition stop condition t low 80 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 clock output timing clkout t clh t cll t cycl t clf t clr interrupt input timing nmi intp0 to intp6 t wnih t wnil t with t witl reset input timing reset t wrsh t wrsl 81 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 clock timing x1 t wxh t wxl 1/f x t xf t xr xt1 t xth t xtl 1/f xt data retention characteristics v dd reset nmi (cleared by falling edge) nmi (cleared by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait 82 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 15. package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 - 0.07 p80gc-65-8bt-1 s 1.70 max. r3 ? + 7 ? - 3 ? 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h 83 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f 1.25 14.0 0.2 b 12.0 0.2 m n 0.08 0.145 0.05 p q 0.1 0.05 1.0 j 0.5 (t.p.) k l 0.5 1.0 0.2 i 0.08 s 1.1 0.1 r 3 ? + 4 ? - 3 ? r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t 0.25 u 0.6 0.15 84 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 16. recommended soldering conditions the m pd784225 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. caution soldering conditions for the m pd784224gc- -8bt, m pd784225ygc- -8bt, and m pd784225ygk- -9eu are undetermined because these products are under development. table 16-1. soldering conditions for surface mount type (1) m pD784225GC- -8bt: 80-pin plastic qfp (14 14 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or ir35-00-2 higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or vp15-00-2 higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) exposure limit: 7 days note (after that, prebake at 125 c for 20 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). (2) m pd784224gk- -9eu: 80-pin plastic tqfp (fine pitch) (14 20 mm) m pd784225gk- -9eu: 80-pin plastic tqfp (fine pitch) (14 20 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or ir35-103-2 higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or vp15-103-2 higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). 85 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 appendix a. development tools the following development tools are available for system development using the m pd784225. also see (5) . (1) language processing software ra78k4 assembler package common to 78k/iv series cc78k4 c compiler package common to 78k/iv series df784225 device file common to m pd784225, 784225y subseries cc78k4-l c compiler library source file common to 78k/iv series (2) flash memory writing tools flashpro ii dedicated flash programmer for microcontroller incorporating flash memory (part no.: fl-pr2), flashpro iii (part no.: fl-pr3, pg-fp3) fa-80gc adapter for writing 80-pin plastic qfp (gc-8bt type) flash memory. fa-80gk adapter for writing 80-pin plastic lqfp (gk-be9 type) flash memory. (3) debugging tools ? when ie-78k4-ns in-circuit emulator is used ie-78k4-ns in-circuit emulator common to 78k/iv series ie-70000-mc-ps-b power supply unit for ie-78k4-ns ie-70000-98-if-c interface adapter used when pc-9800 series pc (except notebook type) is used as host machine (c bus supported) ie-70000-cd-if-a pc card and cable when notebook pc is used as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when using ibm pc/at tm or compatible as host machine (isa bus supported) ie-70000-pci-if interface adapter when using pc that incorporates pci bus as host machine ie-784225-ns-em1 emulation board to emulate m pd784225, 784225y subseries np-100gf emulation probe for 100-pin plastic qfp (gf-3ba type) np-100gc emulation probe for 100-pin plastic lqfp (gc-8eu type) ev-9200gf-100 socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect the np-100gc and a target system board on which a 100- pin plastic lqfp (gc-8eu type) can be mounted id78k4-ns integrated debugger for ie-78k4-ns sm78k4 system simulator common to 78k/iv series df784225 device file common to m pd784225, 784225y subseries 86 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 ? when ie-784000-r in-circuit emulator is used ie-784000-r in-circuit emulator common to 78k/iv series ie-70000-98-if-c interface adapter used when pc-9800 series pc (except notebook type) is used as host machine (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at or compatible as host machine (isa bus supported) ie-70000-pci-if interface adapter when using pc that incorporates pci bus as host machine ie-78000-r-sv3 interface adapter and cable used when ews is used as host machine ie-784225-ns-em1 emulation board to emulate m pd784225, 784225y subseries ie-784218-r-em1 ie-784000-r-em emulation board common to 78k/iv series ie-78k4-r-ex3 emulation probe conversion board necessary when using ie-784225-ns-em1 on ie- 784000-r. not necessary when ie-784216-r-em1 is used. ep-78064gf-r emulation probe for 100-pin plastic qfp (gf-3ba type) ep-78064gc-r emulation probe for 100-pin plastic lqfp (gc-8eu type) ev-9200gf-100 socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect the np-100gc and a target system board on which a 100- pin plastic lqfp (gc-8eu type) can be mounted id78k4 integrated debugger for ie-784000-r sm78k4 system simulator common to 78k/iv series df784225 device file common to m pd784225, 784225y subseries (4) real-time os rx78k/iv real-time os for 78k/iv series mx78k4 os for 78k/iv series 87 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 (5) cautions on using development tools ? the id78k4-ns, id78k4, and sm78k4 are used in combination with the df784225. ? the cc78k4 and rx78k/iv are used in combination with the ra78k4 and df784218. ? the fl-pr2, fl-pr3, fa-100gf, fa-100gc, np-100gf, and np-100gc are products made by naito densei machida mfg. co., ltd. (tel: +81-44-822-3813). ? the tgc-100sdw is a product made by tokyo eletech corporation. for further information, contact daimaru kogyo, ltd. tokyo electronic division (tel: +81-3-3820-7112) osaka electronic division (tel: +81-6-6244-6672) ? for third-party development tools, see the 78k/iv series selection guide (u13355e) . ? the host machine and os suitable for each software are as follows: host machine pc ews [os] pc-9800 series [windows] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k4 note cc78k4 note id78k4-ns C id78k4 sm78k4 C rx78k/iv note mx78k4 note note dos-based software 88 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 appendix b. related documents documents related to device document name document no. japanese english m pd784224, 784225, 784224y, 784225y data sheet u12376j this document m pd78f4225, 78f4225y data sheet u12377j planned m pd784225, 784225y subseries users manual - hardware planned planned m pd784225y subseries special function register table planned C 78k/iv series users manual - instruction u10905j u10905e 78k/iv series instruction table u10594j C 78k/iv series instruction set u10595j C 78k/iv series application note - software basics u10095j u10095e documents related to development tools (users manuals) document name document no. japanese english ra78k4 assembler package operation u11334j u11334e language u11162j u11162e ra78k series structured assembler preprocessor u11743j u11743e cc78k4 c compiler operation u11572j u11572e language u11571j u11571e ie-78k4-ns u13356j u13356e ie-784000-r u12903j u12903e ie-784218-r-em1 u12155j u12155e ie-784225-ns-em1 u13742j u13742e ep-78064 eeu-934 eeu-1469 sm78k4 system simulator - windows base reference u10093j u10093e sm78k series system simulator external component u10092j u10092e user open interface specification id78k4-ns integrated debugger - pc base reference u12796j u12796e id78k4 integrated debugger - windows base reference u10440j u10440e id78k4 integrated debugger - hp-ux, sunos, reference u11960j u11960e news-os base caution the contents of the above related documents are subject to change without notice. be sure to use the latest edition of a document for designing. 89 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 documents related to embedded software (users manual) document name document no. japanese english 78k/iv series real-time os basics u10603j u10603e installation u10604j u10604e debugger u10364j C 78k/iv series os mx78k4 basics u11779j C other documents document name document no. japanese english semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic c11892j c11892e discharge (esd) semiconductor device quality control/reliability handbook c12769j mei-1202 guide for products related to micro-computer: other companies u11416j C caution the contents of the above related documents are subject to change without notice. be sure to use the latest edition of a document for designing. 90 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. iebus is a trademark of nec corporation. windows is a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. caution this product contains an i 2 c bus interface circuit. when using the i 2 c bus interface, notify its use to nec when ordering custom code. nec can guarantee the following only when the customer informs nec of the use of the interface: purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. 91 m pd784224, 784225, 784224y, 784225y data sheet u12376ej1v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1 92 m pd784224, 784225, 784224y, 784225y the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7d 98. 12 |
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